An EEPROM (hereinafter, also simply “memory”) such as a NAND flash memory performs a data erasing operation on every memory cell block. In the data erasing operation, the memory erases data stored in memory cells included in a memory cell block by extracting a charge from floating gates of the memory cells.
An erase verify check is conducted to verify whether data has been erased. In the erase verify check, a voltage is applied to a cell string in each column and it is determined whether a current flows to the cell string so as to make verification. When no current flows to the cell string in the erase verify check, it is necessary to perform the data erasing operation again. That is, after repeating an erase loop of erasure and verification to erase data, the current sufficiently flows to cell strings in all columns in the erase verify check. To make the entire memory cell blocks including many memory cells into an erasure state, it is normally necessary to repeat the erase loop for a plurality of times.
However, when the number of memory cells in a charge accumulated state (for example, “0” cells storing data “0”) is small and the number of memory cells in a data erased state (for example, “1” cells storing data “1”) is large in a certain memory cell block, the memory cell block possibly and erroneously passes the erase verify check even if the memory cells from which data is insufficiently erased are present therein. This phenomenon is often referred to as “data “1” defect”.